Large scale integrated circuit chips have many input and output connections. In order to accommodate the many connections, manufacturers have produced leadless chip carriers that use a wire bonding process. However, a wire bonding process can be expensive. In order to reduce the complexity and expense of a wire bonding process, manufacturers have increasingly used flip chip technology.
In a flip chip, an integrated circuit carries a pad arrangement on the top surface and is turned upside down (i.e., flipped), thus allowing direct coupling between the pads and matching contacts on the main circuit board or chip carrier. In many typical flip chip circuits, solder or gold bumps are formed on the integrated circuit input/output terminals. The flip chip is directly bonded to a chip carrier or other structure by a solder connection. The input/output pattern that has the soldered or other formed conductive bumps is known as the chip footprint, and is typically designed from the particular design criteria used by one skilled in the art for creating the chip surface connection on the chip itself.
Typically, the flip chip is placed onto a substrate using expensive "pick-in-place" techniques, such as by using a flip chip die bonder. The flip chips are expensive and often the conductive bumps formed at the appropriate input/output contacts are very small and require expensive and complex placement techniques. Additionally, even after the flip chip is placed in its proper position, and the conductive bumps formed as solder or gold/epoxy are in their proper position, the flip chip typically forms a permanent bond with the substrate, making subsequent flip chip removal difficult. This permanent bond is sometimes the result of an underfill that fills the space under the flip chip. The permanent bond could also be the result of solder forming the conductive bumps engaging the substrate. However, often, the flip chip has to be readily removed for replacement with upgrades and/or replacement chips, especially if the original flip chip has become damaged. Even if the flip chip could be readily removed, expensive placement techniques would have to be used.
Some prior art techniques provide alignment features for various flip chip circuits. However, some of these techniques are expensive, complicated, or still require complicated placement techniques. Some of the techniques also make permanent or semi-permanent attachments that make flip chip removal difficult. Examples of such placement and flip chip mounting techniques include EP Patent No. 186,818, which discloses an insulator having holes arranged in a pattern corresponding to that of the contacts, which is placed between a chip and leads for easy alignment. Other U.S. Patents disclose various interposers or spacers for aligning chips such as disclosed in U.S. Pat. Nos. 5,111,279; 5,168,346; 5,347,162; 5,468,681; and 5,489,804, all to Pasch or Pasch, et al.